Design Verification Engineer VLSI
Capgemini Engineering
- Location
- India
- Type
- Full-time
- Posted
- April 26, 2026
Description
JD: Experience: 6 Years, No Freshers Profile will be accepted. Proven working experience within the semiconductor industry in constraint random functional and formal verification • Expertise in hardware verification using SystemVerilog/UVM and Specman E. Experience with communication protocols (inc. Ethernet, CAN/CANXL, SPI). Also experience with AMBA protocols and Infineon internal protocols (e.g., FPI, SRI) • Experience with the following Infineon IPs: XSPI, CANXL, MCMCAN, DRE, LETH, XGETH. •…