Sr Design Verification Engineer - RISC-V

Design Verification Engineer - Senior Level (15 years) Duration: 10-12 Months Contract Locations: Remote (California, oregon, Washington) Pay Range: $80-$85/hr on W2, 40 Hrs Description: The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc. 1) RISC-V architecture knowledge and verification experience 2) VC Formal DPV App (Datapath Verification) which checks the…