STA Engineer

Key Responsibilities: Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions). Perform block‑level and full‑chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios. Own RTL synthesis (Design Compiler/Fusion Compiler/Genus), including constraint setup, QoR optimization, and netlist quality checks. Analyze timing violations, identify root causes, and collaborate with RTL, PD, and architecture teams to resolve issues. Vali…